I was scrolling through the ATmega328P datasheet when I came across a rather fascinating statement about the way in which the data part of the SPI interface is buffered. I can't seem to understand why the double input buffer is necessary. The following statement can be found on page 161 (Datasheet):

The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost.

Can someone please briefly explain to me why the double input buffer is necessary?

1 Answer 1


You have control over when you place a byte in the TX buffer and control over when you read a byte from the RX buffer. You don't have control over when the master sends data to you, though, so somewhere is needed to store that incoming data until you read it. Since the master can start sending another byte before you have read the last one it's critical that the receiving shift register is separate from the register you read the shifted in data from. Only when the complete byte has been shifted in does it get copied to the receive buffer, so that another shifting in can begin.

When transmitting you don't need to worry about that since what you write into the TX buffer is what is about to be shifted out. You don't write anything else until it's time to send the next byte, at which point the TX register is empty anyway.

  • Aaah thanks! I guess this due to the fact that the SPIF flag is only set upon receival of a complete byte? Therefore (if enabled by the SPIE bit in SPCR) the corresponding ISR is only executed after the last bit in that byte. May 21, 2017 at 16:57
  • That is correct.
    – Majenko
    May 21, 2017 at 16:58

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