We're working with these very odd driver chips which are sort of like shift registers except rather than latch the data at the end, the latch needs to happen over the last 'n' clock cycles in parallel with the data being shifted out. Depending on the value of 'n', the data is 'latched' into different registers. Like I said, it's an odd protocol.
Here's an example sending six bytes of data (top row) synced to the latch (bottom row). The latch is HIGH for the last two bits of the data as it's being shifted out.
Time--> 11001100 01010101 10011010 11001011 01001010 10010101 00000000 00000000 00000000 00000000 00000000 00000011
In this example, the latch is synced to the fifth and sixth bit of that last frame (as opposed to the 7th and 8th in the first example) which tells the chip to load this data into a different register.
Time--> 11001100 01010101 10011010 11001011 01001010 10010101 00000000 00000000 00000000 00000000 00000000 00001100
Like I said, it's an odd design, but it basically lets you shoot out data non-stop without having to pause to latch.
Because of having to 'sync' the latch with certain clock cycles in the data, we can't use the standard SPI bus and have to use normal GPIO pins, which of course are substantially slower.
BUT... if I could set up the data for a second SPI bus, then use a buffer to define where the latch is high/low accordingly, that would work.
The issue is I don't know how to, or if it's even possible to sync SPI busses together.
Only thing I can think of is to use one SPI bus as the master and another SPI bus (on the same processor) as a slave, then try to leverage the bi-directional nature of it. But this is just a guess.
I was considering looking into DMA too, but I'm starting with SPI since I know my chip has four SPI busses on it. (Update: I'm starting to think DMA is the way to go here since I now know it is possible to sync two DMA controllers to the same clock.)