I have a computer talking serially to an UNO SPI Master and, beyond it, multiple MEGA Slaves. The slaves never talk back to the master.

I understand it is normal and correct to assert SS LOW to select one slave at a time, such that the master clocks bits via MOSI to the selected slave on the same clock edges the slave sends bits to the master via MISO.

Multiple slaves clocking on MISO would garble the communication back to the master. But what if I don't care? Instead, on a system with a pulled-up MISO pin that does not even have MISO wires attached, what if the master selects all the slaves at once, then clocks a byte out on MOSI with a bit set calling for one specific slave (of 8 possible) to respond to subsequent bytes? That is way faster than the master sorting out with code which slave should get the message originating in the computer. ALL the slaves can check the bit they expect and ignore the subsequent bytes of the SPI message if the bit is CLEAR-- they are not doing anything else at the moment anyway, say.

What is wrong with this idea? Are there electronic issues in the UNO or MEGAs I am not thinking of? Is this done? Why not?

2 Answers 2


What is wrong with this idea?

Nothing, this is perfectly possible. The main advantage is the avoidance of multiple SS lines, reducing pin count and/or decoding hardware.

The SPI main device does not know the number of SPI sub devices, and it will happily sample the level at the MISO pin, whatever you give it.

Each SPI sub device does not know that the other SPI sub devices receive the very same bytes. As you write, if the first byte (or any other protocol detail) tells it to ignore the rest of the transmission, it will.

Are there electronic issues in the UNO or MEGAs I am not thinking of?

You need to read the data sheet to learn about the load of each input of the SPI sub devices, and the guaranteed provided drive capability of each output of the SPI main device, that means SS, SCLK, MOSI. Then make sure the driver can drive all receivers.

Commonly you can connect a two-digit number without any concern.You write that you have eight, so just go ahead.

You can leave the MISO outputs of the SPI sub devices simply unconnected. At the SPI main device make sure you have a pull-up or pull-down resistor on its MISO input.

Is this done?

I have no personal experience or example, but I'm sure it is done.

Why not?

When you actually need responses from the SPI sub devices, you need to do it differently. However, even then you can combine all the MISO outputs of the SPI sub devices with some clever digital logic.

Note: I prefer "main" and "sub", which still match the abbreviations, instead of the old terms of the former century.


The electronic circuit of an SPI work this way, when a slave device is not been selected (i.e. its CS pin is not asserted), its MISO line will be in tri-state output, i.e. it is in a high impedance floating state, electrically disconnect, this allows multiple devices sharing the same MISO bus. For this reason, you can't tie all the slave devices with a single CS pin as all the MISO outputs from the devices will be activated.

If you don't care about the MISO data clocking in from the slave devices, you simple don't connect the MISO pin to the bus.

  • try-state -> Tri-state (as in 3 states). Otherwise, I agree with you.
    – Nick Gammon
    Commented Sep 18, 2023 at 9:13
  • Ops. Thanks for pointing that out.
    – hcheung
    Commented Sep 18, 2023 at 10:12

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