I wanted to compare the debug output of the Arduino Zero when connecting via two different debug paths.

  1. Via the embedded debugger (EDBG) connected to Arduino IDE via USB
  2. Via the JTAG hardware connector J100 to a Black Magic Probe and GDB

The two paths being compared are shown on the Zero Schematic: Snipped image of the JTAG related part of the schematic

Using the Blink.ino compiled for debug, the EDBG works as expected into the Arduino IDE 2.0.4 debugger via USB.

However using the same sketch with the JTAG hardware port to a black magic probe fails to connect, reporting "Target voltage: 1.0V".

rowan@rowan-ThinkPad-X1-Carbon-4th:/tmp/arduino/sketches/1EBCACBEAD6C08902D692E87F523B56E$ arm-none-eabi-gdb Blink.ino.elf 
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Reading symbols from Blink.ino.elf...
(gdb) target extended-remote /dev/ttyACM1
Remote debugging using /dev/ttyACM1
(gdb) monitor jtag_scan
Target voltage: 1.0V
JTAG device scan failed!

Photo of JTAG connection to Zero

The same probe and setup successfully debugs an Arduino Due. Acknowledging different processors on the two boards.

The JTAG connector is correctly oriented.

Is a switching action needed to enable one debug path or the other, or is something else wrong?

Update 2023-04-01: I bought an SWD breakout board so I could get some test leads on without risking bent pins (it took a couple of weeks to arrive). The VREF pin on the Zero is 0V when running the debug version of Blink.ino. In comparison the same test rig connected to Due running debug Blink.ino VREF is 3.3V as expected.

Tracing back the Zero JTAG VREF pin connection on the PCB, the connection is as expected compared to the published PCB Layout. It connects to a pin on the Atmel EDBG chip (IC3). PCB Layout Snippet

At J100 the schematic (snippet above) labels this connection VCC_P3V3. However it seems to connect to VCC_EDBG_P3V3.

I'm going to spend some time with the Atmel EDBG User Guide

Update 2023-04-01 #2: During successful debugging using the USB EDBG to Arduino IDE method, the JTAG (J100) VREF pin remains at 0V.

Update 2023-04-01 #3: Refering to the EDBG datasheet section 5. The pin on the EDBG chip (IC3) to which the JTAG Vref pin is connected is (K9) EDBG_TCK. Noting the orientation is inverted compared to the PCB image. EDBG VBGA Package Pinout EDBG_TCK is described as "JTAG Test Clock pin for EDBG device", and is in the EDBG manufacturing programming group of pins.

OK, it's clear to me now, that this isn't the JTAG I was looking for, I'll write it up as an answer.

  • I’ve been trying out Chat GPT-4. Here’s what it has to say about the error message: …There could be several reasons why the JTAG device scan failed. Some possible reasons include a faulty connection between the test probe and the target device, incorrect configuration settings in the test probe, or an issue with the JTAG interface of the target device. … you could try checking the connections between the test probe and the target device, verifying that the test probe is configured correctly, and ensuring that the JTAG interface of the target device is functioning properly…
    – RowanP
    Mar 16, 2023 at 12:19

1 Answer 1


I believe the problem occured because I assumed that J100 on the schematic is the populated JTAG interface. Tracing through the schematics and PCB layout indicate that J100 on the schematic is CN2 on the PCB layout (the JTAG interface with no headers populated). J301 on the schematic is the JTAG interface with headers installed, called CN1 on the PCB layout Zero PCB Layout

J301 (CN1) is for programming the EDBG chip. J301 CN1 Schematic snippet

J100 (CN2) breaks out JTAG target interface pins, but does not have header installed. J100 CN2

Arduino Zero Image

Contrary to the schematic, looking at J100 (CN2) on the PCB laypout and also by visual inspection of the physical PCB VREF pin 1 does not seem to have any connection to +3V3.

Top View: J100 (CN2) VREF pin detail - top Bottom View: J100 (CN2) VREF pin detail - bottom

Counter to the microscope photo evidence, I do read 3.3V (using multimeter) on the square solder pad of the VREF pin, which matches the schematic. I'm having trouble explaining it though. This is a two layer PCB right?

Updated 2/4/2023: My conclusion is that the EDBG JTAG port is not useful with the Black Magic Probe as an alternative to EDBG. The J100 (CN2) port seems like it would be usable if it had headers.

  • Thanks Juraj. That newer pin out is more clearly labeled. I’m still not convinced by the reported +3v3 at J100. I’ll add some microscope photos so you can see what I mean.
    – RowanP
    Apr 1, 2023 at 22:16
  • Re: This is a two layer PCB? No it's not as it turns out. Note the green traces in the photo above. Assumption is that J100 (CN2) VREF is making its connection to +3V3 on the middle layer and it's been missed out of the PCB layout diagram.
    – RowanP
    Apr 3, 2023 at 23:28

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