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I have a teensy 4.0 which runs at 600MHz, and is double superscaler (i.e. can execute two instructions per clock cycle, sometimes). I need an interrupt to happen faster than every microsecond. I've calculated that it's possible for the processor to run the my code at that speed with some reasonable overhead. Can TimerOne (or similar) be set to produce an interrupt more than once per microsecond?

Thanks in advance.

  • Are you talking about the library TimerOne or about the timer itself? – chrisl Feb 10 at 21:32
  • @chrisl well I've been using the TimerOne library but if the only way to get a faster interrupt is to not use that library then that's OK with me. – Jachdich Feb 10 at 22:04
  • forum.pjrc.com – Juraj Feb 12 at 17:59
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You can use the TeensyTimerTool for this. It provides a generic interface to the hardware timers (TMR, GPT, PIT) and 20 software timers. Since the coupling of the timer peripherals to the ARM core is rather inefficient, the software timers might be a better fit for sub micro second interrupts. If you prefer the hardware timers I suggest to use a GPT timer (also supported by the lib). You can configure it to use a 150MHz clock instead of the standard 24MHz clock. So something like 2MHz interrupt rate should be feasible.

Documentation can be found here: https://github.com/luni64/TeensyTimerTool/wiki

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