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According to Ken Shirrif's article, Ken Shirriff's blog - Secrets of Arduino PWM (and the same article on the Arduino pages - Secrets of Arduino PWM), under the section Varying the timer top limit: phase-correct PWM, Timer2 supports the Phase Correct PWM using OCR2A top, which gives OCR2A 50% duty cycle.

There is an example using OCR2A as TOP, where OC2A has a duty cycle fixed at 50% and OC2B has a user-specified duty cycle:

  pinMode(3, OUTPUT);
  pinMode(11, OUTPUT);
  TCCR2A = _BV(COM2A0) | _BV(COM2B1) | _BV(WGM20);
  TCCR2B = _BV(WGM22) | _BV(CS22);
  OCR2A = 180;
  OCR2B = 50;

On the Arduino Duemilanove, these values yield:

  • Output A frequency: 16 MHz / 64 / 180 / 2 / 2 = 347.2Hz
  • Output A duty cycle: 50%
  • Output B frequency: 16 MHz / 64 / 180 / 2 = 694.4Hz
  • Output B duty cycle: 50 / 180 = 27.8%

However, in the ATmega328 data sheet, whilst this behaviour is explained for Timer1 (13.9.4 Phase Correct PWM Mode):

If OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.

in the Timer2 section, there is no reference to it, in 15.7.4 Phase Correct PWM Mode. Except in 15.7.3 Fast PWM Mode

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform generated will have a maximum frequency of fOC2 = fclk_I/O/2 when OCR2A is set to zero. This feature is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.

Likewise, there is no mention for Timer0 in 12.7.4 Phase Correct PWM Mode, apart from 12.7.3 - Fast PWM Mode, where it states:

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC0x to toggle its logical level on each compare match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero. This feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode.

Why is that? Is it actually true, that which Ken Shirriff describes, or not? Is it truly a secret, that is not mentioned in the datasheet, and if [it is] not [mentioned], then why not? Why would Atmel keep it a secret?

Or... am I missing, or misunderstanding, something in the datasheet?

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