I'm trying to interface with a master I2C device that doesn't exactly follow the normal I2C protocol.
The only difference really is in the read request. A "normal" I2C read operation looks like this ([M]aster, [S]lave):
S | SLA+R | ACK | Data | Ack | Data ...some number of bytes... Nack | P ^M ^M ^S ^S ^M ^S ^M ^M
But this device expects to do a read like this:
S | SLA+R | ACK | Data | Ack | Data | Ack | Data | Ack | P ^M ^M ^S ^M ^S ^S ^M ^S ^M ^M
Essentially a read request goes to the slave device, and then the master sends an 8-bit register address, and then the master expects 2 data bytes back from the slave with the Master responding with an ACK on both.
I've been able to set up a master device to do this style of protocol pretty easily by just manipulating the I2C registers directly. But I can't seem to find a way to get the slave device to accept that it is going to receive a data byte after it has been selected by a SLA+R, which leads to a bus contention problem and the slave not giving the master an ACK.
Is this possible to do with the built in I2C hardware on the Atmel chips? Is there any alternative if it can't (bit-banging)?