Assuming that by "Mega" you mean the Mega 2560, see sections 15.2.4 and 15.2.5 of the 2/2014 datasheet referring to the External Interrupt Flags and Pin Change Interrupt flags:
When an edge or logic change on the INT7:0 pin triggers an interrupt
request, INTF7:0 becomes set (one). If the I-bit in SREG and the
corresponding interrupt enable bit, INT7:0 in EIMSK, are set (one),
the MCU will jump to the interrupt vector. The flag is cleared when
the interrupt routine is executed. Alternatively, the flag can be
cleared by writing a logical one to it. These flags are always cleared
when INT7:0 are configured as level interrupt.
It is not clear from the above when specifically "The flag is cleared when the interrupt routine is executed" happens. It wouldn't be much use if it happened on ISR entry so I'll take a guess that it happens on return from interrupt, in which case the flags would be available to read in the ISR. An experiment would be in order, here. These flag registers are known to the compiler as EIFR and PCIFR, respectively.